ESMT

F25L008A

Elite Semiconductor Memory Technology Inc.

Publication Date: May. 2007

9/31

Instructions

Instructions are used to Read, Write (Erase and Program), and

configure the F25L008A. The instruction bus cycles are 8 bits

each for commands (Op Code), data, and addresses. Prior to

executing any Byte-Program, Sector-Erase, Block-Erase, or

Chip-Erase instructions, the Write-Enable (WREN) instruction

must be executed first. The complete list of the instructions is

provided in Table 5. All instructions are synchronized off a high to

low transition of CE . Inputs will be accepted on the rising edge

of SCK starting with the most significant bit. CE must be driven

low before an instruction is entered and must be driven high after

the last bit of the instruction has been shifted in (except for Read,

Read-ID and Read-Status-Register instructions). Any low to high

transition on CE , before receiving the last bit of an instruction

bus cycle, will terminate the instruction in progress and return the

device to the standby mode.

Instruction commands (Op Code), addresses, and data are all

input from the most significant bit (MSB) first.

TABLE 5: DEVICE OPERATION INSTRUCTIONS

Bus Cycle

1

2

3

4

5

6

Cycle Type/

Operation

1,2

Max

Freq

Read

03H

Hi-Z

Hi-Z

X

High-Speed-Read

0BH

Hi-Z

Hi-Z

X

X

X

Sector-Erase

20H

Hi-Z

Hi-Z

-

-

Block-Erase (64K Byte)

D8H

Hi-Z

Hi-Z

-

-

Chip-Erase

6

60H

C7H

Hi-Z

-

-

-

-

-

-

-

-

Byte-Program

5

02H

Hi-Z

Hi-Z

Hi-Z

Auto-Address-Increment-wor

d programming (AAI)

ADH

Hi-Z

Hi-Z

Hi-Z

Read-Status-Register

(RDSR)

05H

Hi-Z

X

-

Note

7

-

Note

7

-

Note

7

Enable-Write-Status-Registe

r

(EWSR)

8

50H

Hi-Z

-

-

-

-

-

-

-

-

Write-Status-Register

(WRSR)

8

01H

Hi-Z

Data

Hi-Z

-

-

-.

-

-

-

Write-Enable (WREN)

11

06H

Hi-Z

-

-

-

-

-

-

-

-

Write-Disable (WRDI)

04H

Hi-Z

-

Read-Electronic-Signature

(RES)

ABH

Hi-Z

X

13H

-

-

-

-

-

-

20H(Top)

Jedec-Read-ID (JEDEC-ID)

10

9FH

Hi-Z

X

8CH

X

21H(Bottom)

X

14H

-

-

8CH

13H

Read-ID (RDID)

Hi-Z

Hi-Z

X

13H

X

8CH

Enable SO to output RY/BY#

Status during AAI (EBSY)

70H

Hi-Z

-

-

-

-

-

-

-

-

Disable

SO

to

output

RY/BY#

Status during AAI (DBSY)

80H

Hi-Z

-

-

-

-

-

-

-

-

1.

2.

3.

One bus cycle is eight clock periods.

4.

5.

Prior to any Byte-Program, Sector-Erase , Block-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be

executed.

6.

To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be

programmed.

7.

The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .

8.

The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction

of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both