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HT46R01 Datasheet(PDF) 19 Page - Holtek Semiconductor Inc |
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HT46R01 Datasheet(HTML) 19 Page - Holtek Semiconductor Inc |
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19 / 60 page ![]() HT46R01/HT46R02/HT46R03 Rev. 1.00 19 September 21, 2007 Timer Registers - TMR0, TMR1 The timer registers are special function registers located in the Special Purpose Data Memory and is the place where the actual timer value is stored. These registers are known as TMR0 or TMR1, depending upon which de- vice is used. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH at which point the timer overflows and an internal interrupt signal is gener- ated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH, the preload register must first be cleared to all zeros. It should be noted that after power-on, the preload regis- ters will be in an unknown condition. Note that if the Timer/Event Counters are in an OFF condition and data is written to their preload registers, this data will be im- mediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data registers during this period will re- main in the preload registers and will only be written into the actual counter the next time an overflow occurs. Timer Control Registers - TMR0C, TMR1C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. For devices with only one timer, the single Timer Control Register is known as TMR0C while for devices with more than one timer, there are two Timer Control Regis- ters, known as TMR0C and TMR1C. It is the Timer Con- trol Register together with its corresponding timer registers that control the full operation of the T M R 1 T 1 E T i m e r / E v e n t C o u n t e r M o d e C o n t r o l T 1 O N P r e l o a d R e g i s t e r T i m e r / E v e n t C o u n t e r D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t P F D T 1 M 1 T 1 M 0 2 ¸ f S Y S / 4 R T C O s c i l l a t o r M U X T 1 S 8-bit Timer/Event Counter 1 Structure - HT46R02 and HT46R03 T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r T M R 0 C A l l D e v i c e s b 7 E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e T 0 E T 0 O N T 0 M 0 T 0 M 1 T i m e r p r e s c a l e r r a t e s e l e c t T 0 P S C 2 0 0 0 0 1 1 1 1 b 0 T 0 P S C 2 T 0 P S C 1 T 0 P S C 0 T 0 P S C 1 0 0 1 1 0 0 1 1 T 0 P S C 0 0 1 0 1 0 1 0 1 T i m e r R a t e 1 : 1 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4 1 : 1 2 8 T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e O p e r a t i n g m o d e s e l e c t T 0 M 1 0 0 1 1 T 0 M 0 0 1 0 1 n o m o d e a v a i l a b l e e v e n t c o u n t e r m o d e t i m e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e T 0 S T i m e r c l o c k s o u r c e 1 : R T C 0 : f S Y S |
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