Layout

Layout Guideline

• Both input and output capacitors must be placed as close to the pins of the device as possible.

• It is recommended to bypass the IN pin to ground with a 1-μF to 10-μF capacitor in parallel with a 0.1-μF small ceramic

capacitor. The loop area formed by the bypass capacitor connection, the IN pin, and the GND pin of the system must be

as small as possible.

• It is required to place a decoupling 1-μF to 50-μF capacitor at the output. A small 1-μF ceramic capacitor in parallel is

recommended to filter the noise and improve the output transient performance.

Layout Example

DNC

IN

DNC

GND

NC

NC

OUT

NR

VREF To ADC

Figure 15. Layout Example

TPR70

Low-Noise, Low-Drift, Precision Voltage Reference

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DA20231202A2