SH3100 datasheet(28/80 Pages) SEMTECH

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SH3100

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POWER MANAGEMENT

Address(hex): 18

Description

(R/W) Configures ADC, DAC and

comparator configuration, as

well as setting the overall device

mode

Default Value: 0000 0100

Reset Event: P, W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initiate ADC

Conversion

Comparator

polarity

Device mode

DAC Clock post-scaler

DAC Enable

Bit No.

Description

Bit Value

Value Description

[7]

Initiate ADC Conversion

Setting this bit initiates an ADC conversion

The conversion is completed within 1500 cycles of the internal

DAC clock, the rate of which is determined by the

DACClkPostScaler in this register, and the rate of the HFDCO.

ADC conversion completion is signaled by the ADCDone flag in

the InterruptStatus register

[6]

Comparator Polarity

General-purpose comparator output is used directly

General-purpose comparator output is inverted

[5:3]

DeviceMode

THIS REGISTER IS FUSE

INITIALIZED

000

001

011

100

101

Normal mode – PWM pin can be controlled by setting the

PWMDutyCycle

Switched boost regulator mode – PWM pin controls an external

inductor/capacitor network

Switched buck regulator mode

LDO Mode – PWM pin is driven by internal LDO

Fan control mode – PWM pin is controlled as described in the

PWM section

Note that this register may not be changed if the

App-specificFuseWP bit in the WriteProtects register is set

[2:1]

DACClkPostScaler

DACClk is 32.768 kHz (ADC Conversion in 45 ms)

DACClk is HFDCO/8 (ADC Conversion in 11264 cycles of HFDCO

period)

DACClk is HFDCO/16 (ADC Conversion in 22528 cycles of

HFDCO period)

DACClk is HFDCO/32 (ADC conversion in 45056 cycles of

HFDCO period)

[0]

DAC Enable

General-purpose DAC & comparator are powered down

General-purpose DAC & comparator are enabled

SH3100 Datasheet(PDF) 28 Page - Semtech Corporation

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