SH3100 datasheet(30/80 Pages) SEMTECH

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SH3100

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POWER MANAGEMENT

Address(hex): 20

Description

(R/W) Sets up CLK0

Default Value: 0011 0000

Reset Event: P, W (bit 7)

Reset Event: P, W, B (bits 6:0)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CLK0Supply

CLK0 HF/LF

CLK1=CLK0

CLK0Enable

CLK0 post-scaler

Bit No.

Description

Bit Value

Value Description

[7]

CLK0 supply

CLK0 pad is supplied by VDD. When VDD drops below VBO,

CLK0 ceases

CLK0 pad is supplied by VBAK

[6]

CLK0 HF/LF

CLK0 is derived from the post-scaled HFDCO

CLK0 is set to 32.768 kHz

[5]

CLK1 = CLK0

CLK1 is treated completely independently from CLK0. Phase

relationship can not be guaranteed

CLK1 is set to run at the same frequency as CLK0, with or

without inversion. CLK1 and CLK0 transition together, and

operate as in-phase or complementary clock outputs

[4]

CLK0Enable

If any interrupt is enabled in the InterruptEnable register, then

setting CLK0 to 0 disables CLK0. The clock resumes whenever

any enabled interrupt activates

CLK0 is enabled unless in AutoClkDetect mode and CLKIN has

stopped

[2:0]

CLK0 PostScaler

THIS REGISTER IS FUSE

INITIALIZED

000

001

010

011

100

101

110

111

CLK0 frequency = HFDCO frequency

CLK0 frequency = HFDCO/2

CLK0 frequency = HFDCO/4

CLK0 frequency = HFDCO/8

CLK0 frequency = HFDCO/16

CLK0 frequency = HFDCO/32

CLK0 frequency = HFDCO/64

CLK0 frequency = HFDCO/128

This register is ignored if the CLK0 HF/LF bit is set

Note that this register may not be changed if the

App-specificFuseWP bit in the WriteProtects register is set

SH3100 Datasheet(PDF) 30 Page - Semtech Corporation

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