6

LR645

8-Lead SOIC (Narrow Body) Package Outline (LG/TG)

4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch

1

8

Seating

Plane

Gauge

Plane

L

L1

L2

E

E1

D

e

b

A

A2

A1

Seating

Plane

A

A

Top View

Side View

View B

View B

θ1

θ

Note 1

(Index Area

D/2 x E1/2)

View A-A

h

h

Note 1

Symbol

A

A1

A2

b

D

E

E1

e

h

L

L1

L2

θ

θ1

Dimension

(mm)

MIN

1.35

0.10

1.25

0.31

4.80

5.80

3.80

1.27

BSC

0.25

0.40

1.04

REF

0.25

BSC

NOM

----

4.90

6.00

3.90

-

-

-

-

MAX

1.75

0.25

1.50

0.51

5.00

6.20

4.00

0.50

1.27

JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.

Drawings not to scale.

Note 1:

This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a

mold, or an embedded metal or marked feature.