HT49CV3 datasheet(11/44 Pages) HOLTEK

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HT49RV3/HT49CV3

Rev. 1.30

March 20, 2007

Bit No.

Label

Function

RMTVF

Remote control timer overflow interrupt flag (1=indicates that an overflow has occurred;

0=indicates that an overflow has not occurred)

RTF

Real time clock interrupt flag (1=indicates that an RTC interrupt has occurred;

0=indicates that an RTC interrupt has not occurred)

RMT0F

Remote control timer rising edge interrupt flag (1=indicates that a rising edge interrupt has oc-

curred; 0=indicates that a rising edge interrupt has not occurred)

RMT1F

Remote control timer falling edge interrupt flag (1=indicates that a falling edge interrupt has

occurred; 0=indicates that a falling edge interrupt has not occurred)

ERTI

Controls the real time clock interrupt (1=enable; 0=disable)

5~7

Unused bit, read as

²0²

MFIS (29H) Register

External interrupts are triggered by an edge transition of

INT0 or INT1 (configuration option: high to low, low to

high, low to high or high to low), and the related interrupt

request flag (EIF0; bit 4 of the INTC0, EIF1; bit 5 of the

INTC0) is set as well. After the interrupt is enabled, the

stack is not full, and the external interrupt is active, a

subroutine call to location 04H or 08H occurs. The inter-

rupt request flag (EIF0 or EIF1) and EMI bits are all

cleared to disable other maskable interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 6 of the INTC0), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 0CH occurs. The related inter-

rupt request flag (T0F) is reset, and the EMI bit is

cleared to disable other maskable interrupts.

Timer/Event Counter 1 is operated in the same manner

but its related interrupt request flag is T1F (bit 4 of the

INTC1) and its subroutine call location is 10H.

The Serial Interface interrupt is initialized by setting the

interrupt request flag (SIF; bit 5 of the INTC1), which is

caused by completely receiving or transferring 8 bits of

data from a serial interface. After the interrupt is en-

abled, and the stack is not full, and the SIF bit is set, a

subroutine call to location 14H occurs. The related inter-

rupt request flag (SIF) is reset and the EMI bit is cleared

to disable further maskable interrupts.

The multi-function interrupt is initialized by setting the in-

terrupt request flag (MFF; bit 6 of the INTC1), which is

caused by a regular real time clock signal, or caused by

a rising edge of RMT, or caused by a falling edge of

RMT, or caused by an RMT overflow. After the interrupt

is enabled, and the stack is not full, and the MFF bit is

set, a subroutine call to location 18H occurs. The related

interrupt request flag (MFF) is reset and the EMI bit is

cleared to disable further maskable interrupts.

During the execution of an interrupt subroutine, other

maskable interrupt acknowledgments are all held until

the

²RETI² instruction is executed or the EMI bit and the

related interrupt control bit are both set to 1 (if the stack

is not full). To return from the interrupt subroutine,

²RET²

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt 0

04H

External interrupt 1

08H

Timer/Event Counter 0 overflow

0CH

Timer/Event Counter 1 overflow

10H

Serial Interface interrupt

14H

Multi-function interrupt

18H

The RMT overflow interrupt flag (RMTVF; bit 0 of the

MFIS), real time clock interrupt flag (RTF; bit 1 of the

MFIS), the RMT rising edge interrupt flag (RMT0F; bit 2

of the MFIS) and the RMT falling edge interrupt flag

(RMT1F; bit 3 of the MFIS) indicate that a related inter-

rupt has occurred. After reading these flags, these flags

will not be cleared automatically, they should be cleared

by the user.

The serial interface interrupt is indicated by the interrupt

flag (SIF; bit 5 of the INTC1), that is caused by receiving or

transferring a complete 8-bit data transfer between the

HT49RV3/HT49CV3 and an external device. After the in-

terrupt is enabled (by setting ESII; bit 1 of the INTC1), and

the stack is not full, a subroutine call to location 14H oc-

curs.

The Timer/Event Counter 0 interrupt request flag (T0F),

external interrupt 1 request flag (EIF1), external inter-

rupt 0 request flag (EIF0), enable Timer/Event Counter0

interrupt bit (ET0I), enable external interrupt 1 bit (EEI1),

enable external interrupt 0 bit (EEI0), and enable master

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