HT82J30R datasheet(9/47 Pages) HOLTEK

9 / 47 page

HT82J30R/HT82J30A

Rev. 1.00

December 20, 2006

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but

also changes the status register.

Status Register

- STATUS

This 8-bit register contains the zero flag (Z), carry flag

(C), auxiliary carry flag (AC), overflow flag (OV), power

down flag (PDF), and watchdog time-out flag (TO). It

also records the status information and controls the op-

eration sequence.

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

tion, operations related to the status register may

give different results from those intended. The TO

flag can be affected only by system power-up, a WDT

time-out or executing the

²CLR WDT² or ²HALT² in-

struction. The PDF flag can be affected only by exe-

cuting the

²HALT² or ²CLR WDT² instruction or

during a system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

Interrupt

The microcontroller provides two external interrupts, an

internal timer/event counter overflow interrupt, an A/D

converter end-of-conversion interrupt and two SPI inter-

rupts. The interrupt control registers INTC and INTC1

both contains the interrupt control bits to set the en-

able/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked by clearing the EMI bit. This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flags are recorded. If a certain

interrupt requires servicing within the service routine,

the programmer may set the EMI bit and the corre-

sponding bit of INTC or INTC1 to allow interrupt nesting.

If the stack is full, the interrupt request will not be ac-

knowledged, even if the related interrupt is enabled, un-

til the SP is decreased. If immediate service is desired,

the stack has to be prevented from becoming full.

All interrupts have a wake-up capability. As an interrupt

is serviced, a control transfer occurs by pushing the pro-

gram counter onto the stack and then branching to sub-

routines at a specified location in the program memory.

Only the program counter is pushed onto the stack. If

the contents of the register or status register are altered

by the interrupt service program, which corrupts the de-

sired control sequence, the programmer should save

these contents first.

External interrupts are triggered by a high to low transi-

tion on pins INT0 or INT1 which will in turn set the re-

lated interrupt request flag, which is bit 4 of INTC or bit 6

of INTC1. When the respective interrupt is enabled, the

stack is not full and the external interrupt is active, a sub-

routine call to location 004H or 018H will occur. The ex-

ternal interrupt request flag and EMI bits will cleared to

disable other interrupts.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag (bit

5 of INTC), caused by a timer overflow. When the inter-

rupt is enabled, the stack is not full and the timer/event

Bit No.

Label

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

1AC

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF

PDF is cleared by system power-up or executing the

²CLR WDT² instruction.

PDF is set by executing the

²HALT² instruction.

5TO

TO is cleared by system power-up or executing the

²CLR WDT² or ²HALT² instruction.

TO is set by a WDT time-out.

6~7

Unused bit, read as

²0²

Status (0AH) Register

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