HT82J30R datasheet(21/47 Pages) HOLTEK

21 / 47 page

HT82J30R/HT82J30A

Rev. 1.00

December 20, 2006

mentioned in the description.

Two corresponding registers, SBCR and SBDR are

unique to the serial interface and provide control, status,

and data storage.

· SBCR_A, SBCR_B: Serial bus control register

Bit7 (CKS) clock source selection: fSIO=fSYS/4,

select as 0

Bit6 (M1), Bit5 (M0) master/slave mode and baud rate

selection

M1, M0: 00

® MASTER MODE, BAUD RATE= fSIO

® MASTER MODE, BAUD RATE= fSIO/4

® MASTER MODE, BAUD RATE= fSIO/16

® SLAVE MODE

· Bit4 (SBEN) ® serial bus enable/disable (1/0)

¨ Enable: (SCS dependent on CSEN bit)

Disable

® enable: SCK, SDI, SDO, SCS=0

(SCKB=

²0²) and waiting for writing data to SBDR

(TXRX buffer)

Master mode: write data to SBDR (TXRX buffer)

start transmission/reception automatically

Master mode: when the data has been transferred,

set TRF

Slave mode: when an SCK (and SCS dependent on

CSEN) is received, data in the TXRX buffer is

shifted-out and data on SDI is shifted-in.

¨ Disable: SCK (SCK), SDI, SDO, SCS floating

Bit3 (MLS)

® MSB or LSB (1/0) shift first control bit

Bit2 (CSEN)

® serial bus selection signal enable/dis-

able (SCS), when CSEN=0, SCSB is floating.

Bit1 (WCOL)

® this bit is set to 1 if data is written to

the SBDR register (TXRX buffer) when data is

transferred, writing will be ignored if data is written

to SBDR (TXRX buffer) when data is transferred.

Bit0 (TRF)

® data transferred or data received

used to generate an interrupt.

Note: data reception is still in operation when the

MCU enters the Power-down mode.

· SBDR_A, SBDR_B: Serial bus data register

Data written to SBDR

® write data to the TXRX buffer

only

Data read from SBDR

® read from SBDR only

Operating Mode description:

Master transmitter: clock transmission and data I/O

started by writing to SBDR

Master clock transmission initiated by writing to SBDR

Slave transmitter: data I/O started by clock reception

Slave receiver: data I/O started by clock reception

D 7 / D 0

D 6 / D 1

D 5 / D 2

D 4 / D 3

D 3 / D 4

D 2 / D 5

D 1 / D 6

D 0 / D 7

S D O _ A , S D O _ B

D 7 / D 0

D 6 / D 1

D 5 / D 2

D 4 / D 3

D 3 / D 4

D 2 / D 5

D 1 / D 6

D 0 / D 7

S D I _ A , S D I _ B

S C K _ A , S C K _ B

S C S _ A , S C S _ B

S B C R _ A , S B C R _ B

D E F A U L T

S B D R _ A , S B D R _ B

D E F A U L T

N o t e : " U " m e a n s u n c h a n g e d .

C K S

M 1

M 0

S B E N

M L S

C S E N

W C O L

T R F

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

S B C R : S E R I A L B U S

C O N T R O L R E G I S T E R

S B D R : S E R I A L B U S

D A T A R E G I S T E R

t C S _ S K

t S P I C K

t C S _ S K

SPI Serial Interface

There are two SPI interfaces, with each interface containing four basic signals and pins. These are SDI (serial data in-

put), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note that each of these pin names will be

suffixed with either an A or B to denote which SCI interface is being used, however to minimise repetition, this will not be

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