5

© 2006 Semtech Corp.

www.semtech.com

SC488

POWER MANAGEMENT

Parameter

Conditions

25°C

-40°C to 85°C

Units

Min

Typ

Max

Min

Max

Gate Drives

Shoot-Thru Protection

DH or DL Rising

30

ns

DL Pull-Down Resistance

DL Low

0.8

Ω

DL Sink Current

V

3.1

A

DL Pull-Up Resistance

DL High

2

Ω

DL Source Current

V

1.3

A

DH Pull-Down Resistance

DH Low, BST - LX = 5V

2

Ω

DH High, BST - LX = 5V

2

Ω

DH Sink/Source Current

V

1.3

A

VTT Pull-Up Resistance

VTTS < REF

0.25

Ω

VTT Pull-Down Resistance

VTTS > REF

0.32

Ω

VTT Peak Sink/Source

2.8

A

Electrical Characteristics (Cont.)

Notes:

1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage.

2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET.

3) clks = switching cycles, consisting of one high side and one low side gate pulse.

4) Guaranteed by design.

5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.

6) VTT soft-start ramp rate is limited to 5.5mV/μs typical. If the VDDQ/2 ramp rate is slower than 5.5mV/μsec, the VTT soft-start ramp will follow the VDDQ/2

ramp.

7) See Shoot-Through Delay Timing Diagram below.

8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device

is activated, reducing the resistance to 2Ω (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost

resistor.

9) Provided operation below T

increases with temperature, and by available source voltage (typically VDDQ/2).

tplhDL

tplhDH

LX

DL

DL

DH

Shoot-Through Delay Timing Diagram