Pad Description

Pad No.

Pad Name

I/O

Description

51, 1

CC1, CC2

I

External capacitor pin, for double voltage and half voltage circuit use

2

VO15N

O

Half voltage circuit output pin

3

VEE

¾

Double voltage circuit output pin

4~7

COM0~COM3

O

LCD common outputs

8~39

SEG0~SEG31

O

LCD segment outputs

40

CS

I

Chip selection input with pull-high resistor.

When the CS is logic high, the data and command, read from or written to the

HT1620 are disabled. The serial interface circuit is also reset. But if the CS is

at logic low level and is input to the CS pad, the data and command transmis-

sion between the host controller and the HT1620 are all enabled.

41

RD

I

READ clock input with pull-high resistor.

Data in the RAM of the HT1620 are clocked out on the falling edge of the RD

signal. The clocked out data will appear on the DATA line. The host controller

can use the next raising edge to latch the clocked out data.

42

WR

I

WRITE clock input with pull-high resistor.

Data on the DATA line are latched into the HT1620 on the rising edge of the

WR signal.

43

DATA

I/O

Serial data input/output with pull-high resistor

44

VSS

¾

Negative power supply, Ground

45

OSCO

O

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

generate a system clock.

46

OSCI

I

47

VDD

¾

Positive power supply

48

IRQ

O

Time base or WDT overflow flag, NMOS open drain output

49, 50

BZ, BZ

O

2kHz or 4kHz tone frequency output pair (tri-state output buffer)

Absolute Maximum Ratings

Storage Temperature ............................

Operating Temperature...........................

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

HT1620

Rev. 1.30

4

March 27, 2007