SN74LS195A

5

DEFINITIONS OF TERMS

SETUP TIME(ts) —is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.

AC WAVEFORMS

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays and

Clock Pulse Width

Figure 2. Master Reset Pulse Width, Master Reset

to Output Delay and Master Reset to Clock

Recovery Time

CONDITIONS: MR = H

*Q0 STATE WILL BE DETERMINED BY J AND K INPUTS.

1.3 V

1.3 V

1.3 V

1.3 V

CLOCK

OUTPUT

PE

Qn = Pn

Qn* = Qn–1

trel

trel

ts(L)

ts(H)

LOAD PARALLEL DATA

LOAD SERIAL DATA

SHIFT RIGHT

1.3 V

CONDITIONS: PE = L

PO = P1 = P2 = P3 = H

CONDITIONS: MR = H

*J AND K SET–UP TIME AFFECTS Q0 ONLY

PE

J & K

P0 P1 P2 P3

CLOCK

OUTPUT*

CLOCK

CLOCK

OUTPUT

OUTPUT

ts(H)

th(L) = 0

th(H) = 0

th(H) = 0

ts(H)

th(L) = 0

ts(L)

tPHL

tPLH

ts(L)

MR

trec

tPHL

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tW

CONDITIONS: J = PE = MR = H

K = L

tW

1.3 V

Figure 3. Setup (ts) and Hold (th) Time for Serial Data

(J & K) and Parallel Data (P0, P1, P2, P3)

Figure 4. Setup (ts) and Hold (th) Time for PE Input

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