M58PR256J datasheet(9/114 Pages) STMICROELECTRONICS

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M58PR256J, M58PR512J

Description

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Description

The M58PR256J and M58PR512J are 256 Mbit (16 Mbit ×16) and 512 Mbit (32 Mbit ×16)

non-volatile Flash memories, respectively. They are referred to as M58PRxxxJ in the rest of

the document unless otherwise specified.

The M58PRxxxJ may be erased electrically at Block level and programmed in-system on a

Word-by-Word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V

VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to

speed up factory programming.

The M58PRxxxJ has a uniform Block architecture and is based on a Multi-Level cell

technology.

The M58PR256J has an array of 128 Blocks, and is divided into 32 Mbit banks. There are 8

banks each containing 16 Blocks of 128 KWords.

The M58PR512J has an array of 256 Blocks, and is divided into 64 Mbit banks. There are 8

Banks each containing 32 Blocks of 128 KWords.

Each Block contains 256 Program Regions of 1 KByte each, that are divided into 32

Segments of 16 Words. Each Segment is split into two halves (A and B), according by the

value on Address Input A3.

The memory map is illustrated in Figure 2, and the Main Array architecture in Figure 3.

The Multiple Bank Architecture allows Dual Operations, while programming or erasing in

one bank, read operations are possible in other banks. Only one bank at a time is allowed to

be in program or erase mode. It is possible to perform burst reads that cross bank

boundaries. The bank architecture is summarized in Table 2, and the memory maps are

shown in Figure 2.

Each Block can be erased separately. Erase can be suspended, in order to perform a

program or read operation in any other Block, and then resumed. Program can be

suspended to read data at any memory location except for the one being programmed, and

then resumed. Each Block can be programmed and erased over 100,000 cycles using the

supply voltage VDD. There is a Buffer Enhanced Factory programming command available

to speed up programming.

Program and erase commands are written to the Command Interface of the memory. An

internal Program/Erase Controller takes care of the timings necessary for program and

erase operations. The end of a program or erase operation can be detected and any error

conditions identified in the Status Register. The command set required to control the

memory is consistent with JEDEC standards.

The device supports Synchronous Burst Read and Asynchronous Read from all Blocks of

the memory array; at power-up the device is configured for Asynchronous Read. In

Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to

108 MHz. The Synchronous Burst Read operation can be suspended and resumed.

The device features an Automatic Standby mode and Deep Power-Down mode. When the

bus is inactive during Asynchronous Read operations, the device automatically switches to

the Automatic Standby mode. In this condition the power consumption is reduced to the

standby value and the outputs are still driven.

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