MNSC140CORE datasheet(54/88 Pages) FREESCALE

54 / 88 page

MSC8122 Technical Data, Rev. 13

2-20

Freescale Semiconductor

Specifications

2.5.7

TDM Timing

Table 2-20.

TDM Timing

No.

Characteristic

Expression

1.1 V Core

1.2 V Core

Units

Min

Max

Min

Max

300

TDMxRCLK/TDMxTCLK

TC1

—

301

TDMxRCLK/TDMxTCLK high pulse width

(0.5

± 0.1) × TC

—

302

TDMxRCLK/TDMxTCLK low pulse width

(0.5

± 0.1) × TC

—

303

TDM receive all input set-up time

1.3

—

1.3

—

304

TDM receive all input hold time

1.0

—

1.0

—

305

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

active2,3

2.8

—

2.8

—

306

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

—

10.0

—

8.8

307

All output hold time4

2.5

—

2.5

—

308

TDMxTCLK high to TDmXTDAT/TDMxRCLK output high

impedance2,3

—

10.7

—

10.5

309

TDMxTCLK high to TDMXTSYN output valid2

—

9.7

—

8.5

310

TDMxTSYN output hold time4

2.5

—

2.5

—

Notes:

Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.

Values are based on 20 pF capacitive load.

When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details.

Values are based on 10 pF capacitive load.

Figure 2-12.

TDM Inputs Signals

Figure 2-13.

TDM Output Signals

TDMxRCLK

TDMxRDAT

TDMxRSYN

300

301

302

303

304

TDMxTCLK

TDMxTDAT

TDMxTSYN

305

306

308

307

300

301

302

310

309

TDMxRCLK

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