LX1675

Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 9

Copyright

© 2004

Rev. 1.2a, 2006-02-16

Multiple Output LoadSHARE™ PWM

TM

®

TH EORY OF O PERAT ION

The

LX1675

is

a

voltage-mode

pulse-width

modulation

controller integrated circuit. The internal ramp generator frequency

is set to 300kHz or 600kHz by the FS logic input. The device has

external compensation, for more flexibility of output current

magnitude.

At power up, the LX1675 monitors the supply voltage at the

VCCL pin. The VIN supply voltage has to be sufficient to produce

a voltage greater that 4.4 volts at the VCCL pin before the

controller will come out of the under-voltage lock-out state. The

soft-start (SS) pin is held low to prevent soft-start from beginning

and the oscillator is disabled and all MOSFETs are held off.

Once the VCCL output is above the UVLO threshold, the soft-

start capacitor begins to be charged by the reference through a

20k

Ω internal resistor. The capacitor voltage at the SS pin rises as a

simple RC circuit. The SS pin is connected to the error amplifier’s

non-inverting input that controls the output voltage.

The output

voltage will follow the SS pin voltage if sufficient charging current

is provided to the output capacitor.

The simple RC soft-start allows the output to rise faster at the

beginning and slower at the end of the soft-start interval. Thus, the

required charging current into the output capacitor is less at the end

of the soft-start interval. A comparator monitors the SS pin voltage

and indicates the end of soft-start when SS pin voltage reaches 95%

current sense comparator senses the MOSFET current 50nS after

the lower MOSFET is switched on in order to reduce inaccuracies

magnitude is 50µA.

at the lower MOSFET drain and the source needs a low impedance

return to get an accurate measurement across the low resistance

comparator outputs a signal to reset the PWM latch on a cycle by

cycle basis until the current limit counter has reached a count of 4.

After a count of 4 the hiccup mode is started.

The soft-start

a 0.1V threshold, hiccup finishes and the circuit soft-starts again.

During hiccup both MOSFETs for that phase are held off. The

Shared Fault, SF logic input, allows all phases to be totally

independent if the SF pin is grounded.

If the SF pin is tied to

VCCL then when one phase has a fault and goes into the hiccup

mode, all phases, including the LDO output will go into the hiccup

mode together.

Hiccup is disabled during the soft-start interval, allowing start up

with maximum current. If the rate of rise of the output voltage is too

fast, the required charging current to the output capacitor may be

higher than the current limit setting. In this case, the peak MOSFET

current is regulated to the limit-current by the current-sense

comparator. If the MOSFET current still reaches its limit after the

soft-start finishes, the hiccup is triggered again. When the output has

a short circuit the hiccup circuit ensures that the average heat

generation in both MOSFETs and the average current is much less

than in normal operation.

Over-current protection can also be implemented using a sense

greater set-point accuracy.

An internal oscillator has a selectable switching frequency of

300kHz or 600kHz set by the FS logic input pin. Connect FS to

ground for 300kHz and to VCCL for 600kHz operation.

CONFIGURATION

The basic principle used in LoadSHARE, in a multiple phase

buck converter topology, is that if multiple, identical, inductors have

the same identical voltage impressed across their leads, they must

then have the same identical current passing through them. The

current that we would like to balance between inductors is mainly

the DC component along with as much as possible the transient

current. All inductors in a multiphase buck converter topology have

their output side tied together at the output filter capacitors.

Therefore this side of all the inductors have the same identical

voltage.

If the input side of the inductors can be forced to have the same

equivalent DC potential on this lead, then they will have the same

DC current flowing. To achieve this requirement, phase 1 will be

the control phase that sets the output operating voltage, under

normal PWM operation. To force the current of phase 2 to be equal

to the current of phase 1, a second feedback loop is used.

Phase 2

has a low pass filter connected from the input side of each inductor.

This side of the inductors has a square wave signal that is

proportional to its duty cycle. The output of each LPF is a DC

(+

some AC) signal that is proportional to the magnitude and duty

cycle of its respective inductor signal. The second feedback loop

will use the output of the phase 1 LPF as a reference signal for an

error amplifier that will compare this reference to the output of the

phase 2 LPF. This error signal will be amplified and used to control

the PWM circuit of phase 2. Therefore, the duty cycle of phase 2

will be set so that the equivalent voltage potential will be forced

across the phase 2 inductor as compared to the phase 1 inductor.

This will force the current in the phase 2 inductor to follow and be

equal to the current in the phase 1 inductor.

There are four methods that can be used to implement the

LoadSHARE feature of the LX1675 in the Bi-Phase mode of

operation.