TMS320VC5510 datasheet(81/90 Pages) TI

81 / 90 page

Electrical Specifications

June 2000 − Revised September 2007

SPRS076O

HR/W

Read Data

HRDY

HCNTL[1:0]

HAS

HCS

HD[15:0]

(read)

E11

E13

Valid (11)

Write Data

HD[15:0]

(write)

E12

E13

E17

E18

Read

Write

HDS

E15

E16

E15

E12

E11

E20

E19

E14

E20

E19

Valid (11)

E10

E14

NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins

must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry

controlled by the HPE bit in the System Register (SYSR).

B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent

with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown

for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is

high HRDY is not driven).

Figure 5−29. EHPI Multiplexed Memory (HPID) Access Read/Write Timings Without Autoincrement

TMS320VC5510 Datasheet(PDF) 81 Page - Texas Instruments

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