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Page 5 of 9

Issue A

LANSDALE Semiconductor, Inc.

ML3356

Figure 6. Application with Self–Adjusting Bias on Data Shaper

RF In

1:2

0.01

20

19

18

17

16

15

14

13

12

11

Data

Out

5.0 V

10 k

Car. Det. Out

0 V or 4.0 V

3.3 k

130 k

3.3 k

470

pF

15 k

18 k

150 pF

RF Input

Ground

Data

Output

Comp(+)

Comp(–) Squelch

Status

Squelch

Control

Demod

Out

Demod

Filter

Quad

Input

1

470 k

470 pF

47 k

47 k

0.1

0.1

f = 10.7

1.5

µH

APPLICATION NOTES (continued)

Depending on the external circuit, inverted or noninverted

data is available at Pin 18. Inverted data makes the higher fre-

quency in the FSK signal a “one” when the local oscillator is

above the incoming RF. Figure 5 schematic shows the com-

parator with hysteresis. In this circuit the DC reference volt-

age at Pin 17 is about the same as the demodulated output

voltage (Pin 13) when no signal is present. This type circuit is

preferred for systems where the data rates can drop to zero.

Some systems have a low frequency limit on the data rate,

such as systems using the MC3850 ACIA that has a start or

stop bit. This defines the low frequency limit that can appear

in the data stream. Figure 5 circuit can then be changed to a

circuit configuration as shown in Figure 6. In Figure 6 the ref-

erence voltage for the comparator is derived from the demodu-

lator output through a low pass circuit where

τ is much lower

than the lowest frequency data rate. This and similar circuits

will compensate for small tuning changes (or drift) in the

quadrature detector.

Squelch status (Pin 15) goes high (squelch off) when the

input signal becomes greater than some preset level set by the

resistance between Pin 14 and ground. Hysteresis is added to

the circuit externally by the resistance from Pin 14 to Pin 15.

Legacy Applications Information