GL824C datasheet(39/56 Pages) GENESYS

39 / 56 page

GL824/GL824C USB 2.0 On-The-Go Controller

Page 39

Thr

Data Hold Time following IOR-

6.5.8 Reset Timing

Extrstz

Trst

Figure 6.11 - Timing Diagram of Reset

Parameter

Description

Minimum

Unit

Remark

Trst

This active low signal is used by the system

to reset the chip; the active low pulse should

be at least 1us wide.

6.5.9 ATA/ ATAPI

The GL824 complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:

DMA (Direct Memory Access) data transfer:

DMA data transfer means of data transfer between device and host memory without host processor

intervention.

- Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE

DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a

Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET

DEVICE data, this data transfer protocol shall be used for the data transfers associated with these

commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)

- Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA,

READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is

enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these

commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please

refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)

Following listed the symbols and their respective definitions that are used in the timing diagram:

GL824C Datasheet(PDF) 39 Page - GENESYS LOGIC