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GL824C Datasheet(PDF) 21 Page - GENESYS LOGIC

Part # GL824C
Description  USB 2.0 On-The-Go Controller
PDF  56 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL824C Datasheet(HTML) 21 Page - GENESYS LOGIC

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GL824/GL824C USB 2.0 On-The-Go Controller
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 21
EXTRST_
42
I
(pd)
External reset
RXD
117
B
(pu)
UART receives data input
TXD
118
O
(pu)
UART transmits data output
I2CK
120
O
(pu)
I
2C bus clock
I2CD
121
B
(pu)
I
2C data
VSEL
124
I
Key voltage detection input
VBAT
125
I
Battery voltage detection input
ATA/ATAPI Interface
Pin Name
Pin#
Type
Description
CS0_
43
O
PESETZ (PCVS2Z)
CS1_
56
O
PESETZ (PCVS1Z)
DA0~2
44,46,45
O
Address 0~2
AINTRQ
50
I
(pd)
IREQZ
DMACK_
51
O
DMACK
AIORDY
52
I
(pu)
IORDY (WAITZ)
DIOR_
53
O
I/O read strobe
DIOW_
54
O
I/O write strobe
DMARQ
55
I
(pd)
DMARQ
DD0~15
58,60,62,64,
66,68,70,
72,71,69,
67,65,63,
61,59,57
B
(pd)
Data 0~15
ARESET_
73
O
ARESET
SDRAM Interface
Pin Name
Pin#
Type
Description
SA1~12
81,79,77,
78,80,82,
83,86,88,
85,90,91
O
SDRAM_A1~A12
SA0/A0
84
O/I
(pd)
SDRAM_A0 / share pin with A0 pin of HOST interface
BA0/WSTS
89
SDRAM_BA0 / share pin with write status pin of HOST
interface
BA1/RSTS
87
O
SDRAM_BA1 / share pin with read status pin of HOST
interface
CKE
92
O
SDRAM_CKE
RAS_/RE_
93
O/I
(pu)
SDRAM_RAS / share pin with read enable pin of HOST
interface



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