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CLK

ADS5474

CLK

0.1

F

m

Clock

Source

ClockCommonMode

V

-

90

85

80

75

70

65

50

0

1

5

2

3

4

60

55

f =400MSPS

V

=3V

S

CLK

PP

230MHz

351MHz

70MHz

10MHz

ClockCommonMode

V

-

75

70

65

50

0

1

5

2

3

4

60

55

f =400MSPS

V

=3V

S

CLK

PP

230MHz

351MHz

70MHz

10MHz

ADS5474

SLAS525 – JULY 2007

For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The

differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a

differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications

because the board level clock jitter is superior.

Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In

the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of

clock noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow

clock frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR

degradation. Figure 43 demonstrates a recommended method for converting a single-ended clock source into a

differential clock; it is similar to the configuration found on the evaluation board and was used for much of the

characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.

Figure 43. Differential Clock

The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-k

Ω resistors. It is

recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to

clock common-mode variation (as shown in Figure 44 and Figure 45). Additionally, the internal ADC core uses

both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.

Performance degradation as a result of duty cycle can be seen in Figure 46.

Figure 44. SFDR versus Clock Common Mode

Figure 45. SNR versus Clock Common Mode

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