AN610

DS00610A-page 2

© 1995 Microchip Technology Inc.

A framing procedure involves looking for the header

portion of the EDID table which is a byte of 00H

followed by 6 bytes of FFH and another byte of 00H. A

framing routine would continue to clock data from the

24LC21 until this unique header has been found. At

this point, the current location in the EDID table has

been

determined

and

the

controller

has

now

synchronized itself with the device. Care must be

taken while using the device in the transmit only mode

to prevent noise on the SCL pin, as a falling edge seen

on this pin will immediately send the part into the

bi-directional mode. In a DDC1-only monitor, SCL is

not connected to the VGA connector, but must still be

FIGURE 1:

TRANSMIT ONLY MODE

FIGURE 2:

DEVICE INITIALIZATION FOR TRANSMIT-ONLY MODE

SCL

SDA

VCLK

Bit1

(LSB)

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Null

Bit8

Bit

Bit7

(MSB)

SCL must remain high for transmit-only mode

SCL

SDA

VCLK

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15

SDA at high impedance for 9 clock cycles

Bit8

Bit7

Bit6

Bit5 Bit4

Valid data begins on 10th clock