R2880

R

R

FAST ETHERNET RISC PROCESSOR

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 5

REV 1.0 Jun. 12 2007

1.

Features

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CPU Core

- RDC’s proprietary RISC architecture

- Five-stage pipeline architecture

- Operation frequency: 100MHz

- Supports an 8K-byte uniform cache

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ROM/RAM/SDRAM Controller and

Addressing Space

- Supports 16-bit data bus width

- Flash ROM/SRAM control interface

- SDRAM control interface

- 16M addressing space

- 64K-byte I/O space

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Two Independent DMA Controllers

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Interrupt Controller

- Provides 8 maskable external interrupt channels

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Counter/ Timers

- Three independent 16-bit timers

- Timer 1 can be programmed as a watchdog timer

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High Performance UART Ports

- Supports 2 high performance UARTs with

send/receive 16-byte FIFOs

- Programmable baud rate generators

- The data rates are programmable from 50 to

460.8K baud (max. to 1Mbps)

- The character options are programmable for 1 start

bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8

data bits

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RDC Debug Tool Support

- RDC debug tool with a JTAG-like interface

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General Programmable I/O

- 48 programmable I/O ports

- Pins individually configurable to input or output

mode

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Two 10/100M Fast Ethernet MAC Ports

- IEEE 802.3u MII interface

- IEEE 802.3x flow control in full-duplex mode

- Internal loop-back self-test circuit support

- Descriptor architecture for packet TX/RX

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PCI Control Interface Support

- Supports up to 5 PCI masters

- Speed up to 33MHz

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Two Card Bus Interface Support

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A Green Product

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Package Type

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208-pin PQFP

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225-ball LFBGA

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Operating Temperature : 0 ~ 70 ℃