R8610

RISC DSP Communication

32 Bit RISC Micro Controller

Specifications subject to change without notice, contact your sales representatives for the most update information.

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REV 1.1

Sep. 05 2007

1.

Features

n

Embedded RISC Controller

–

Full 32 bit RISC architecture

–

Supports diverse operation systems, including

MS-Windows, Linux and most of the popular 32 bit

RTOS

–

6-stage pipeline

–

Operation frequency: 133 MHz

–

Supports MMU function which includes 32 TLB

entries

n

MAC Controller

–

Supports two-port 10/100 Fast Ethernet MAC

–

IEEE 802.3u MII interface

–

IEEE 802.3x flow control in full-duplex mode

–

Descriptor architecture for packet TX/RX

n

Interrupt Controller

–

Provides two 8259 compatible interrupt controllers

which are cascaded internally

–

Independent programmable level/edge-triggered

interrupt channels

–

Serial IRQ supported

n

DMA Controller

–

Provides two 8237 DMA compatible controllers

which are cascaded internally

–

4 channels for 8-bit DMA transfer and 3

channels for 16 bit transfer

n

Two USB 2.0 Host Port Support

–

Supports HS, FS and LS

n

FIFO UART Port

–

A high performance UART port with transmit and

receive FIFOs

–

Supports the programmable baud rate generator

with the data rates from 50 to 115,200 bps

–

The character options are programmable for 1 start

bit; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8

data bits

n

PCI Control Interface

–

Supports PCI Rev 2.1 specification

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32-bit bus interface

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Supports PCI clock at 33 MHz

–

Supports PCI host

–

Supports PCI master/ slave

–

–

Supports up to 3 external master devices on PCI

–

Provides four PCI interrupt channels

n

LPC ( Low Pin Count ) Bus Interface

–

LPC revision 1.0 compliant

–

Supports LPC/FWH ( Firmware Hub ) compliant

interfaces

–

Provides the interface to connect an LPC/FWH

Flash ROM or Super I/O chip

–

Supports LPC DMA

–

Supports serial IRQ

–

Supports 8/16/32-bit transfer size

–

Supports bus master request in DMA channel 4

n

X-Bus Interface

–

Provides the interface to boot ROM BIOS & DOC

(Disk On Chip).

–

Supports 8/16 bit data width

–

Provides ROMCS_n for booting from X-bus Flash

ROM

–

Supports from 64K byte to max 16M byte ROM

space addressing

–

Supports two independent and programmable CSs

( Chip Selects )

n

SDRAM Control Interface

–

PC100/ PC133 compliant

–

Supports 16-bit data bus width

–

Supports speeds up to 133 MHz and above

–

Supports maximum 128 MB memory space

n

On-Chip L1 16KB Cache

–

Unified instructions and data cache

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Supports write through for cache write policy

–

Snooping mechanism support for data coherence

between main memory and cache

–

Direct map

n

General Programmable I / O

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Supports 58 programmable I/ O pins