AME, Inc.

Rev.A.01

7

AT209S

PCI Arbiter and Clock Buffer

PLL

PCICLKOUT

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLKI

Figure 2. Clock Buffer Block Diagram

Output-to-Output Skew

Since the PCICLKOUT and the PCICLK(1-4) outputs are identical, they all start at the same time, but different loads

cause them to have different rise times and different times crossing the measurement thresholds.

If all outputs are equally loaded, zero phase difference will maintained from PCICLKI to all outputs.

If applications requiring zero output-output skew, all the outputs must equally loaded.

If the PCICLK(1-4) outputs are less loaded than PCICLKOUT, PCICLK(1-4) outputs will lead it; and if the PCICLK(1-4)

is more loaded than PCICLKOUT, PCICLK(1-4) will lag the PCICLKOUT.