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RT8801 Datasheet(PDF) 13 Page - Richtek Technology Corporation

Part # RT8801
Description  Multi-Phase PWM Controller for CPU Core Power Supply with Serial Programming Interface
PDF  23 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT8801 Datasheet(HTML) 13 Page - Richtek Technology Corporation

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RT8801
Preliminary
13
DS8801-04
August 2007
www.richtek.com
All brandname or trademark belong to their owner respectively
Application Information
RT8801 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT8801 and its companion MOSFET driver RT9607/
RT9607A provides high quality CPU power and all
protection functions to meet the requirement of modern
VRM.
Voltage Control
RT8801 senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VIDDAC provides the reference voltage for
VRD10.X compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of error
amplifier and the error signal is used as the control signal
of pulse width modulator. The PWM signals of different
channels are generated by comparison of EA output and
split-phase sawtooth wave. Power stage transforms VIN
to output by PWM signal on-time ratio.
Current Balance
RT8801 senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call
“active
voltage positioning
” can reduce the output voltage ripple
at load transient and the LC filter size.
Fault Detection
The chip detects FB for over voltage. The
“hiccup mode”
operation of over current protection is adopted to reduce
the short circuit current. The inrush current at the start up
is suppressed by the soft start circuit through clamping
the pulse width and output voltage.
Phase Setting and Converter Start Up
RT8801 interfaces with companion MOSFET drivers (like
RT9619, RT9607 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VDD
and DVD trip). The channel is enabled if the pin voltage is
1.2V less than VDD. Tie the PWM to VDD and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Sensing Setting
RT8801 senses the current flowing through inductor via
its DCR for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
Figure 1. Current Sense Circuit
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
CSN
C
X
L
C
R
V
I
I
DCR
V
C
R
DCR
L
=
×
=
×
=
L
DCR
R
RCSN
GMx
Ix
C
+
-
VC



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