RT8805 datasheet(13/15 Pages) RICHTEK

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RT8805

Preliminary

DS8805-01 November 2005

www.richtek.com

operated under or over maximum (~125

°C) operation

rating.

Layout Considerations

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability.

First, place the PWM power stage components. Mount

all the power components and connections in the top layer

with wide copper areas. The MOSFETs of Buck, inductor,

and output capacitor should be as close to each other as

possible. This can reduce the radiation of EMI due to the

high frequency current loop. If the output capacitors are

placed in parallel to reduce the ESR of capacitor, equal

sharing ripple current should be considered. Place the

input capacitor directly to the drain of high-side MOSFET.

In multi-layer PCB, use one layer as power ground and

have a separate control signal ground as the reference of

the all signal. To avoid the signal ground is effect by noise

and have best load regulation, it should be connected to

the ground terminal of output. Furthermore, follows below

guidelines can get better performance of IC :

1. A multi-layer printed circuit board is recommended.

2. Use a middle layer of the PC board as a ground plane

and making all critical component ground connections

through vias to this layer.

3. Use another solid layer as a power plane and break this

plane into smaller islands of common voltage levels.

4. Keep the metal running from the PHASE terminal to

the output inductor short.

5. Use copper filled polygons on the top and bottom circuit

layers for the phase node.

6. The small signal wiring traces from the LGATE and

UGATE pins to the MOSFET gates should be kept

short and wide enough to easily handle the several

Amperes of drive current.

7. The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Position those components close to their

pins with a local GND connection, or via directly to the

ground plane.

≈

board space is the limiting constraint, current can be

pushed as high as 40A per phase, but these designs

require heat sinks and forced air to cool the MOSFETs,

inductors and heat dissipating surfaces.

MOSFETs

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching

frequency, the capability of the MOSFETs to dissipate

heat, and the availability and nature of heat sinking and

air flow.

Package Power Dissipation

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of two

drivers in the controller package, the total power dissipated

by both drivers must be less than the maximum allowable

power dissipation for the VQFN package. Calculating the

power dissipation in the drivers for a desired application

is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the

IC beyond the maximum recommended operating junction

temperature of 125

°C. The maximum allowable IC power

dissipation for the 3x3 VQFN package is approximately

1.47W at room temperature.

According below equations at two phases operation, it’s

clear to describe that the junction temperature of the chip

is directly proportional to the total CISS (including CUGATE

and CLGATE) of all external MOSFETs.

PD = ( CUGATE x VBOOT-PHASE2 x f ) + ( CLGATE x VCC2 x f ) +

TJ = TA + (

θJA x PD )

(

χ is the minor factor and could be ignored)

For example, according to the application we evaluated

on board, the CUGATE = 1nF, CLGATE = 5nF (dual MOSFETs

in parallel), VCC = 12V, VBOOT-PHASE = 12V, and operation

frequency = 300kHz.

1nF x 122 x 300kHz + 2 x 5nF x 122 x 300kHz =

475mW / PHASE

TJ = 30

°C+ 68°C/W x 0.475W x 2 = 94.6°C

That means the junction temperature is most likely to be

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