ADV7403

Rev. SpA | Page 11 of 24

Pin No.

Mnemonic

Type

Function

3

INT

O

Interrupt. This pin can be active low or active high. When SDP/CP status bits change,

this pin triggers. The set of events that triggers an interrupt is under user control.

4

HS/CS

O

HS is a Horizontal Synchronization Output Signal (SDP and CP modes). CS is a Digital

Composite Synchronization Signal (and can be selected while in CP mode).

99

VS

O

Vertical Synchronization Output Signal (SDP and CP modes).

98

FIELD/DE

O

FIELD is a Field Synchronization Output Signal (all interlaced video modes). This

pin also can be enabled as a Data Enable signal (DE) in CP mode to allow direct

connection to a HDMI/DVI Tx IC.

81, 19

SDA1, SDA2

I/O

SDA2 is the data line for the VBI readback port.

82, 16

SCLK1, SCLK2

I

Control port and SCLK2 is the clock line for the VBI data readback port.

80

ALSB

I

set to Logic 0 sets the address for a write to control port of 0x40 and the readback

address for the VBI port of 0x21. ALSB set to a logic high sets the address for a write to

control port of 0x42 and the readback address for the VBI port of 0x23.

78

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV7403 circuitry.

36

LLC1

O

LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz to 140 MHz

for ADV7403KSTZ-140; 12.825 MHz to 110 MHz for ADV7403BSTZ-110.

38

XTAL

I

Input Pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,

28.63636 MHz clock oscillator source to clock the ADV7403.

37

XTAL1

O

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an

external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7403. In

crystal mode the crystal must be a fundamental crystal.

46

ELPF

O

The recommend external loop filter must be connected to this ELPF pin.

70

TEST0

NC

This pin should be left unconnected or alternaltely tie to AGND.

59

TEST1

O

This pin should be left unconnected.

15

SFL/SYNC_OUT

O

Subcarrier Frequency Lock (SFL). This pin contains a serial output stream, which can

be used to lock the subcarrier frequency when this decoder is connected to any

Analog Devices digital video encoder. SYNC_OUT is the sliced sync output signal

available only in CP mode.

64

REFOUT

O

Internal Voltage Reference Output.

65

CML

O

Common-Mode Level Pin (CML) for the internal ADCs.

61, 62

CAPY1, CAPY2

I

ADC Capacitor Network.

68, 69

CAPC1, CAPC2

I

ADC Capacitor Network.

67

BIAS

O

External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between pin

and ground.

86

HS_IN/CS_IN

I

Can be configured in CP mode to be either a digital HS input signal or a digital CS

input signal used to extract timing in a 5-wire or 4-wire RGB mode.

85

VS_IN

I

VS Input Signal. Used in CP mode for 5-wire timing mode.

79

DE_IN

I

Data Enable Input Signal. Used in 24-bit digital input port mode (for example,

processing 24-bit RGB data from a DVI Rx IC).

35

DCLK_IN

I

Clock Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit

RGB data from a DVI Rx IC) and also in digital CVBS input mode.

52

SOG

I

Sync on Green Input. Used in embedded sync mode.

77

SOY

I

Sync on Luma Input. Used in embedded sync mode.