RT9644 datasheet(13/17 Pages) RICHTEK

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Preliminary

DS9644/A-01 August 2007

www.richtek.com

RT9644/A

DS(ON)

OCSET

L(MAX)

period and no other fault occurs, then the Fault Counter

is cleared to 0. If a fault occurs prior to the Fault Reset

Counter reaching 9 x Tss period, then the Fault Reset

Counter is set back to zero.

The RT9644/A will immediately shut down when the Fault

Counter reaches a count of 4. When attempting to restart

a faulted regulator, the RT9644/A will follow the preset

start up sequencing. If a regulator is already in regulation,

then it will not be affected by the start up sequencing.

VDDQ Overcurrent Protection

The OCP function monitors output current by using upper

MOSFET RDS(ON). The OCP function cycles soft-start

function in a hiccup mode. Over-current triggering level

can be arbitrarily set by adjusting ROCSET. An Internal 20

µA

current sink makes a voltage drop across ROCSET from

VIN. When VPHASE is lower than VOCSET, OCP function

initializes soft-start cycles. The OCP funcion will be

triggered as inductor current reach :

To prevent OC form tripping in normal operation, ROCSET

must be carefully chosen with :

1. Maximum RDS(ON) at highest junction temperature

2. MInimum IOCSET from specification table

3. IL(MAX) > IOUT(MAX) +

∆ IL /2

∆IL = inductor ripple current

Feedback Compensation

Figure 3 highlights the voltage-mode control loop for a

synchronous buck conv erter. Figure 4 shows the

corresponding Bode plot. The output voltage (VOUT) is

regulated to the reference voltage. The error amplifier EA

output (COMP) is compared with the oscillator (OSC)

sawtooth wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output filter (L and COUT).

The modulator transfer function is the small-signal transfer

function of VOUT/COMP. This function is dominated by a

DC gain and the output filter (L and COUT), with a double

pole break frequency at FP_LC and a zero at FZ_ESR.

The DC gain of the modulator is simply the input voltage

(VIN) divided by the peak-to-peak oscillator voltage %VOSC.

The compensation network consists of the error amplifier

EA and the impedance networks ZIN and ZFB. The goal of

the compensation network is to provide a closed loop

transfer function with the highest DC gain, the highest

0dB crossing frequency (FC) and adequate phase margin.

Typically, FC in range 1/5 to 1/10 of switching frequency

is adequate. The higher FC is, the faster dynamic response

is. A phase margin in the range of 45

°C to 60° C is

desirable. The equations below relate the compensation

network poles, zeros and gain to the components (R1,

R2, R3, C1, C2, and C3) in Figure 4.

The break frequency FLC and FESR are expressed as

Equation (1) and (2) respectively.

(1)

(2)

OUT

Z_ESR

OUT

P_LC

ESR

(3)

(4)

(5)

(6)

)

(R1

OSC

∆V

OSC

Driver

REF

PWM

Comparator

E/A

REF

OUT

COMP

ESR

PHASE

OUT

Figure 3

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