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High Speed CMOS Logic – 54HC05

Rev 1.0

22/04/19

DC Electrical Characteristics Continued (Voltages Referenced to GND)

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

VIN = VIL or VIL

│IOUT│≤ 20µA

0.1

0.1

0.1

4.5V

VIN = VIL or VIL

│IOUT│≤ 4.0mA

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

VOL

6.0V

VIN = VIL or VIL

│IOUT│≤ 5.2mA

0.26

0.33

0.40

V

Maximum Input

Leakage Current

IIN

6.0V

VIN = VCC or GND

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Leakage

Current

ICC

6.0V

VIN = VCC or GND

IOUT = 0µA

1

10

40

µA

Maximum Three-

State Leakage

Current

IOZ

6.0V

Output in high

impedance state,

VIN = VIL or VIL

VOUT=VCC or GND

±0.5

±5

±10

µA

AC Electrical Characteristics5

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

90

115

135

4.5V

18

23

27

Maximum Propagation

Delay, Input A or B to

Output Y

(Figure 1,2)

tPLH, tPHL

6.0V

CL = 50pF,

Input

tr = tf = 6ns

15

20

23

ns

2.0V

75

95

110

4.5V

15

19

22

Maximum Output

Transition Time,

Any Output

(Figure 1,2)

tTHL

6.0V

CL = 50pF,

Input

tr = tf = 6ns

13

16

19

ns

 

LIMITS

5. Not production tested in die form, characterized by chip design and tested in package.

6. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Maximum Input

Capacitance

CIN

6.0V

-

10

10

10

pF

Maximum Three-State

Output Capacitance

COUT

6.0V

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance Per Buffer

6

CPD

5.0V

TJ = 25°C,

VEE = 0V

4

pF

Capacitance5