High Speed CMOS Logic – 54HC05

 

 

 

 

Hex Inverter Gate with Open-Drain Outputs in bare die form

Rev 1.0

22/04/19

Output Drive Capability: 10 LSTTL Loads*

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1550 x 1300

61 x 51

µm

mils

Minimum Bond Pad Size

106 x 106

4.17 x 4.17

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Operating Voltage Range: 2V to 6V

Function compatible with 54LS05

High Noise Immunity CMOS process

Full Military Temperature Range.

Features:

The 54HC05 hex inverter gate is fabricated on a 2.5µm 5V

CMOS process combining high speed LSTTL performance

with CMOS low power. The device contains six

independent inverters with open-drain outputs and perform

the Boolean function Y = Ᾱ . Device outputs can connect

with other open-drain outputs to form active LOW wired-OR

or active HIGH wired-AND logic functions. Open-drain

outputs need pull-up resistors to perform correctly*. Inputs

are compatible with standard CMOS outputs; with pull-up

resistors, they are compatible with LSTTL outputs.  

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

1550 (61)

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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