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Capacitance7

Advanced CMOS Logic – 74AC244

Rev 1.0

24/04/19

PARAMETER

SYMBOL

VCC

CONDITIONS

TYPICAL

UNITS

Maximum Input

Capacitance

CIN

5.0V

TJ = 25°C

4.5

pF

Power Dissipation

Capacitance

(Per Buffer/Driver)

CPD

5.0V

TJ = 25°C,

CL = 50pF,

F = 1MHz

45

pF

Switching Waveforms

Figure 1 – Propagation Delay - Input 1A or 2A to Output 1Y or 2Y

7. Not production tested in die form, characterized by chip design and tested in package.

AC Electrical Characteristics7

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

tPLH

9.0

10.0

10.0

tPHL

3.3V ±0.3

CL = 50pF

9.0

10.0

10.0

ns

tPLH

7.0

7.5

7.5

Propagation Delay

1A to 1Y or 2A to 2Y

(Figure 1)

tPHL

5V ±0.5

CL = 50pF

7.0

7.5

7.5

ns

tPZH

10.5

11.0

11.0

tPZL

3.3V ±0.3

CL = 50pF

10.0

11.0

11.0

ns

tPZH

7.0

8.0

8.0

Output Enable Time

OE to 1Y or 2Y

(Figure 2)

tPZL

5V ±0.5

CL = 50pF

8.0

8.5

8.5

ns

tPHZ

10.0

10.5

10.5

tPLZ

3.3V ±0.3

CL = 50pF

10.5

11.5

11.5

ns

tPHZ

9

9.5

9.5

Output Disable Time

OE to 1Y or 2Y

tPLZ

5V ±0.5

CL = 50pF

9

9.5

9.5

ns