PM6680 datasheet(24/49 Pages) STMICROELECTRONICS

24 / 49 page

Device description

PM6680

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7.3

Output ripple compensation and loop stability

In a classic Constant On Time control, the system regulates the valley value of the output

voltage and not the average value, as shown in Figure 28 In this condition, the output

voltage ripple is source of a DC static error.

To compensate this error, an integrator network can be introduced in the control loop, by

connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections

respectively) pin through a capacitor CINT as in Figure 30

Figure 30.

Circuitry for output ripple compensation

The integrator amplifier generates a current, proportional to the DC errors between the FB

voltage and Vr, which decreases the output voltage in order to compensate the total static

error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for the

output ripple. In steady state, the voltage on COMP1/COMP2 pin is the sum of the reference

voltage Vr and the output ripple (see Figure 30). In fact when the voltage on the COMP pin

reaches Vr, a fixed Ton begins and the output increases.

For example, we consider Vout = 5V with an output ripple of

∆V = 50mV. Considering

CINT >> CFILT, the CINT DC voltage drop VCINT is about 5V-Vr+25mV = 4.125V. CINT assures

an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output

ripple, with a DC value of Vr + 25mV = 925mV.

For more details about the output ripple compensation network, see the Section 7.13.6:

Closing the integrator loop on page 37 in the Design guidelines.

In steady state the FB pin voltage is about Vr and the regulated output voltage depends on

the external divider:

Equation 4

Vrr

arra

atto

orr

CIINNTT

RIINNTT

CFFIILLTT

COOUUTT

COMP PIN

VOLTAGE

OUTPUT

VOLTAGE

I=gm(V1-Vr)

∆V

VCCIINNTT

ROOUUTT

R11

R22

OUT

-------

⎝⎠

⎛⎞

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