PM6680 datasheet(44/49 Pages) STMICROELECTRONICS

44 / 49 page

Device description

PM6680

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possible. Place the synchronous diode D near the LS MOSFET. Connect the LS

MOSFET drain to the switching node with a short trace.

●

Place input capacitors near HS MOSFET drain. It is recommended to use the same

input voltage plan for both the switching sections, in order to put together all input

capacitors.

●

Place all the sensitive analog signals (feedbacks, voltage reference, current sense

paths) on the bottom side of the board or in an inner layer. Isolate them from the power

top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in

one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near

the PGND device pin. Place the device on the top or on the bottom size and connect

the exposed pad and the SGND pins to the SGND plan (see Figure 41).

Figure 41.

Current paths, ground connection and driver traces layout

●

As general rule, make the high side and low side drivers traces wide and short. The

high side driver is powered by the bootstrap circuit. It's very important to place

capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for

example on the layer opposite to the device). Route HGATE and PHASE traces as near

as possible in order to minimize the area between them.

The Low side gate driver is powered by the 5V linear regulator output. Placing PGND

and LGATE pins near the low side MOSFETs reduces the length of the traces and the

crosstalk noise between the two sections.

●

The linear regulator output LDO5 is referred to SGND as long as the reference voltage

Vref. Place their output filtering capacitors as near as possible to the device.

●

Place input filtering capacitors near VCC and VIN pins.

●

It would be better if the feedback networks connected to COMP, FB and OUT pins are

"referred" to SGND in the same point as reference voltage Vref. To avoid capacitive

PM6680 Datasheet(PDF) 44 Page - STMicroelectronics