S70GL02GP datasheet(6/14 Pages) SPANSION

6 / 14 page

S70GL-P MirrorBit

TM Flash Family

S70GL-P_00_01 December 4, 2006

Data

Sheet

(Adv an ce

Inf o r m a t io n)

Input/Output Descriptions & Logic Symbol

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Symbol

Type

Description

A26–A0

Input

Address lines for GL02GP

DQ14–DQ0

I/O

Data input/output.

DQ15

I/O

DQ15: Data input/output in word mode .

A-1: LSB address input in byte mode.

CE#

Input

Chip Enable.

OE#

Input

Output Enable.

WE#

Input

Write Enable.

VCC

Supply

Device Power Supply.

VIO

Supply

Versatile IO Input.

VSS

Supply

Ground.

No Connect

Not connected internally.

RY/BY#

Output

Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At

VIL, the device is actively erasing or programming. At High Z, the device is in ready.

BYTE#

Input

Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-

DQ7 are active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15

are active.

RESET#

Input

Hardware Reset. Low = device resets and returns to reading array data.

WP#/ACC

Input

Write Protect/Acceleration Input. At VIL, disables program and erase functions in the

outermost sectors. At VHH, accelerates programming; automatically places device in

unlock bypass mode. Should be at VIH for all other conditions.

RFU

Reserved

Reserved for future use.

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