High Speed CMOS Logic – 54HC125

Quad 3-State Non-inverting Buffers in bare die form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

1350 x 1500

53 x 59

µm

mils

Minimum Bond Pad Size

106 x 106

4.17 x 4.17

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Output Drive Capability: 15 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

Function compatible with 54LS125

High Noise Immunity CMOS process

Full Military Temperature Range.

Rev 1.0

22/04/19

Features:

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

Description

The 54HC125 4-bit non-inverting buffer/line driver is

fabricated on a 2.5µm 5V CMOS process combining high

speed LSTTL performance with CMOS low power. The

device contains four independent buffer gates with 3-state

outputs each controlled by the output enable input. A HIGH

at the output enable input causes the outputs to assume a

HIGH impedance OFF-state. Inputs are compatible with

standard CMOS outputs; with pull-up resistors, they are

compatible with LSTTL outputs.  

Die Dimensions in µm (mils)

1350 (53)

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (100 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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