PCM1609APTR datasheet(12/43 Pages) TI

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SYSTEM CLOCK AND RESET FUNCTIONS

SYSTEM CLOCK INPUT

tw(SCKH)

System Clock

tw(SCKL)

2 V

0.8 V

System Clock

Pulse Cycle

Time(1)

T0005A08

SYSTEM CLOCK OUTPUT

PCM1609A

SLES145A – AUGUST 2005 – REVISED AUGUST 2006

The PCM1609A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma

modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock

frequencies for common audio sampling rates.

Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to

use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is

an excellent choice for providing the PCM1609A system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

(kHz)

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

(1)

2.048

3.072

4.096

6.144

(1)

4.096

6.144

8.192

12.288

(1)

8.192

12.288

16.384

24.576

44.1

(1)

11.2896

16.9344

22.5792

33.8688

(1)

12.288

18.432

24.576

36.864

(1)

24.576

36.864

49.152

(1)

192

24.576

36.864

(1)

This system clock is not supported for the given sampling frequency.

SYMBOL

PARAMETER

MIN

MAX

UNIT

tw(SCKH)

System clock pulse duration, HIGH

tw(SCKL)

System clock pulse duration, LOW

(1)

1/128 fS, ½56 fS, 1/384 fS, 1/512 fS, and 1/768 fS.

Figure 19. System Clock Timing

A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at

either full (fSCKI) or half (fSCKI/2) rate. The SCKO output frequency can be programmed using the CLKD bit of

output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.

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