ADS1174IPAPR datasheet(15/35 Pages) TI

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MODE SELECTION (MODE)

SYNCHRONIZATION (SYNC)

MODE[1:0]

Pins

ADS1174/78

Mode

NewMode

ValidDataReady

DRDY

SPI

Protocol

Frame-Sync

Protocol

NDR-SPI

DOUT

NewMode

ValidDataonDOUT

NDR-FS

Mode

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

The ADS1174/78 supports two modes of operation:

The ADS1174/78 can be synchronized by pulsing the

High-Speed and Low-Power. These modes offer

SYNC pin low and then returning the pin high. When

optimization of speed or power. The mode selection

the pin goes low, the conversion process stops, and

is determined by the status of the digital input MODE

the internal counters used by the digital filter are

pins, as shown in Table 6. The ADS1174/78

reset.

When

the

SYNC

returns

high,

the

constantly monitors the status of the MODE pin

conversion process restarts. Synchronization allows

during operation.

the conversion to be aligned with an external event,

such as a reference timing pulse.

Table 6. Mode Selection

Since the converters of the ADS1174/78 operate in

MODE

MODE SELECTION

MAX fDATA

(1)

parallel from the same master clock and use the

High-Speed

52,734

same SYNC input control, they are, by default, in

Low-Power

10,547

synchronization

with

each

other.

The

sampling

aperture

match

among

the

channels

200ps

(1) fCLK = 27MHz (CLKDIV = 1).

(typical). However, the synchronization of multiple

When using the SPI protocol, DRDY is held high after

ADS1174/78s

somewhat

different.

device

a mode change occurs until settled (or valid) data are

power-on, variations in internal reset thresholds from

ready, as shown in Figure 12 and Table 7.

device

may

result

uncertainty

conversion timing.

In Frame-Sync protocol, the DOUT pins are held low

after a mode change occurs until settled data are

The SYNC pin can be used to synchronize multiple

ready, as shown in Figure 12 and Table 7. Data can

ADS1174/78s

within

the

same

CLK

cycle.

be read from the device to detect when DOUT

Figure 13 illustrates the timing requirement of SYNC

changes to logic 1, indicating valid data.

and CLK in SPI format.

See Figure 14 for the Frame-Sync format timing

requirement.

Figure 12. Mode Change Timing

Table 7. Mode Change

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tNDR-SPI

Time for new data to be ready (SPI)

129

Conversions (1/fDATA)

tNDR-FS

Time for new data to be ready (Frame-Sync)

127

128

Conversions (1/fDATA)

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