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ADS1174IPAPR Datasheet(PDF) 16 Page - Texas Instruments |
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ADS1174IPAPR Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 35 page  www.ti.com CLK DRDY SYNC t NDR t SYN t SCSU t CSHD FSYNC ValidData DOUT SYNC t NDR t SYN CLK t CSHD t SCSU ADS1174 ADS1178 SBAS373 – OCTOBER 2007 After synchronization, indication of valid data In the Frame-Sync format, DOUT goes low as soon depends on the whether SPI or Frame-Sync format as SYNC is taken low; see Figure 14. After SYNC is was used. returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, In the SPI format, DRDY goes high as soon as SYNC DOUT begins to output valid data. For proper is taken low; see Figure 13. After SYNC is returned synchronization, FSYNC, SCLK, and CLK must be high, DRDY stays high while the digital filter is established before taking SYNC high, and must then settling. Once valid data are ready for retrieval, remain running. DRDY goes low. Figure 13. Synchronization Timing for SPI Protocol Table 8. SPI Protocol SYMBOL DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 ns tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 CLK periods tNDR Time for new data to be ready 129 Conversions (1/fDATA) Figure 14. Synchronization Timing for Frame-Sync Protocol Table 9. Frame-Sync Protocol SYMBOL DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 ns tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 CLK periods tNDR Time for new data to be ready 127 128 Conversions (1/fDATA) 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 |
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