ADC10462CIWM datasheet(12/17 Pages) NSC

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Functional Description (Continued)

SIMILAR PRODUCT DIFFERENCES

The ADC1046x, ADC1046x and ADC1066x (where "x" indi-

cates the number of multiplexer inputs) are similar devices

with different specification limits. The differences in these

device families are summarized below.

Device

Family

ILE, TUE,

PSS

THD, SNR,

ENOB

Max.

Conversion

Time

ADC1046x

Guaranteed

900ns

ADC1046x

Guaranteed

900ns

ADC1066x

Guaranteed

466ns

Applications Information

1.0 MODES OF OPERATION

The ADC10461, ADC10462, and ADC10464 have two basic

digital interface modes. Figure 1 and Figure 2 are timing

diagrams for the two modes. The ADC10462 and ADC10464

have input multiplexers that are controlled by the logic levels

on pins S

0 and S1 when S/H goes low. Tables 1, 2 are truth

tables showing how the input channels are assigned.

Mode 1

In this mode, the S/H pin controls the start of conversion. S/H

is pulled low for a minimum of 250 ns. This causes the

comparators in the “coarse” flash converter to become ac-

tive. When S/H goes high, the result of the coarse conver-

sion is latched and the “fine” conversion begins. After 600 ns

(typical), INT goes low, indicating that the conversion results

are latched and can be read by pulling RD low. Note that CS

must be low to enable S/H or RD. CS is internally “ANDed”

with S/H and RD; the input voltage is sampled when CS and

S/H are low, and data is read when CS and RD are low. INT

is reset high on the rising edge of RD.

TABLE 1. Input Multiplexer Programming

ADC10464

Channel

IN0

IN1

IN2

IN3

TABLE 2. Input Multiplexer Programming

ADC10462

Channel

IN0

IN1

Mode 2

In Mode 2, also called “RD mode”, the S/H and RD pins are

tied together. A conversion is initiated by pulling both pins

low. The A/D converter samples the input voltage and

causes the coarse comparators to become active. An inter-

nal timer then terminates the coarse conversion and begins

the fine conversion. 850 ns (typical) after S/H and RD are

pull low, INT goes low, indicating that the conversion is

01110813

FIGURE 3. Block Diagram of the Multistep Converter Architecture

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