LPC2220 datasheet(23/49 Pages) NXP

23 / 49 page

LPC2210_2220_4

Product data sheet

Rev. 04 — 2 October 2007

23 of 49

NXP Semiconductors

LPC2210/2220

16/32-bit ARM microcontrollers with external memory interface

• Optional conversion on transition on input pin or Timer Match signal.

6.12 UARTs

The LPC2210/2220 each contain two UARTs. One UART provides a full modem control

handshake interface, the other provides only transmit and receive data lines.

6.12.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in baud rate generator.

• Standard modem interface signals included on UART1.

• LPC2220 provides enhanced UARTs with fractional baud-rate generators,

mechanism for software ﬂow control, and hardware (CTS/RTS) ﬂow control on UART1

only.

6.13 I2C-bus serial I/O controller

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2210/2220 supports a bit rate up to 400 kbit/s (Fast

I2C-bus).

6.13.1 Features

• Compliant with standard I2C-bus interface.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus may be used for test and diagnostic purposes.

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