LPC2220 datasheet(28/49 Pages) NXP

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LPC2210_2220_4

Product data sheet

Rev. 04 — 2 October 2007

28 of 49

NXP Semiconductors

LPC2210/2220

16/32-bit ARM microcontrollers with external memory interface

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.20.4 External interrupt inputs

The LPC2210/2220 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

6.20.5 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the BANK0

external memory, or to the on-chip static RAM. This allows code running in different

memory spaces to have control of the interrupts.

6.20.6 Power control

The LPC2210/2220 support two reduced power modes: Idle mode and Power-down

mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode, and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.20.7 APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB bus so that they can operate at

the speed chosen for the ARM processor. In order to achieve this, the APB bus may be

slowed down to 1

⁄

2 to

⁄

4 of the processor clock rate. Because the APB bus must work

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