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SM79164 Datasheet(PDF) 13 Page - SyncMOS Technologies,Inc

Part # SM79164
Description  8 - Bit Micro-controller with 64KB flash & 4KB RAM embedded
PDF  25 Pages
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Manufacturer  SYNCMOS [SyncMOS Technologies,Inc]
Direct Link  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

SM79164 Datasheet(HTML) 13 Page - SyncMOS Technologies,Inc

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Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
Watch Dog Timer Register - System Control Register (SCONF, $BF)
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
4. Reduce EMI Function
The SM79164 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
5. Pulse Width Modulation (PWM)
The Pulse Width Modulation (PWM) module contains 1 kind of PWM sub module: PWM. PWM also has four 8-bit channels.
5.1 PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a
PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel
can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available.
The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to deter-
mine the state of each PWM channel output pin.
5.2 PWM Registers - P1CON[7:0], PWMC[7:0], PWMD[7:0]
PWM Registers - Port1 Configuration Register (P1CON, $9B)
PWM[7:0]E: When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset to zero, the
corresponding PWM pin is active as I/O pin. Five bits are cleared upon reset.
PWM Registers - PWM Control Register (PWMC[7:0], $DE ~ $DB, $D6 ~ $D3)
bit-7
bit-0
WDR
Unused
Unused
Unused
Unused
Unused
OME
ALEI
Read / Write:
R/W
-----
R/W
R/W
Reset value:
0
*****
0
0
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
Read / Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
0
0
0
0
0
0
0
bit-7
bit-0
Unused
Unused
Unused
Unused
Unused
PBS[7:0]
PFS[7:0]1
PFS[7:0]0
Read / Write:
-
-
-
-
-
R/W
R/W
R/W
Reset value:
*
***
*
0
0
0



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