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8B10B Datasheet(PDF) 21 Page - Altera Corporation |
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8B10B Datasheet(HTML) 21 Page - Altera Corporation |
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21 / 40 page  Altera Corporation MegaCore Version 7.2 2–7 October 2007 8B10B Encoder/Decoder MegaCore Function User Guide Getting Started 3. Select the mode of operation, either Encoder or Decoder. 4. If you selected Encoder, turn on the Register inputs/outputs check box for a three cycle latency, or turn off the Register inputs/outputs check box for a single cycle latency. 1 The Decoder always has registered inputs and outputs. 5. Click Next (or the Simulation Model tab) to display the simulation setup page (see Figure 2–5). Figure 2–5. Simulation Model Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model file produced by the Quartus II software. The model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. |
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