LPC2387 datasheet(29/47 Pages) NXP

29 / 47 page

LPC2387_1

Product data sheet

Rev. 01.00 — 6 November 2007

29 of 47

NXP Semiconductors

LPC2387

Fast communication chip

7.24.4.3

Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC

oscillator and the flash memory. This saves more power, but requires waiting for

resumption of flash operation before execution of code or data access in the flash memory

can be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60

μs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100

μs flash start-up

time. When it times out, access to the flash will be allowed. The customers need to

reconfigure the PLL and clock dividers accordingly.

7.24.4.4

Power domains

The LPC2387 provides two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the RTC and the Battery RAM.

The 3.3 V (VDD(3V3)) pins power both the on-chip DC-to-DC converter and the I/O pads.

These pins provide the power for the CPU and most of the peripherals. If power is

removed from the VDD(3V3) pins, the CPU and related peripherals stop.

The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

7.25 System control

7.25.1 Reset

Reset has four sources on the LPC2387: the RESET pin, the Watchdog reset, power-on

reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input

pin. Assertion of chip Reset by any source, once the operating voltage attains a usable

level, starts the Wake-up timer (see description in Section 7.24.3 “Wake-up timer”),

causing reset to remain asserted until the external Reset is de-asserted, the oscillator is

running, a fixed number of clocks have passed, and the flash controller has completed its

initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.25.2 Brownout detection

The LPC2387 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this

voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the

VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC2387 when

the voltage on the VDD(3V3) pins falls below 2.65 V. This Reset prevents alteration of the

flash as operation of the various elements of the chip would otherwise become unreliable

due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point

the power-on reset circuitry maintains the overall Reset.

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