DAC8565 datasheet(27/46 Pages) TI

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SERIAL INTERFACE

IOVDD AND VOLTAGE TRANSLATORS

ASYNCHRONOUS RESET

DAC8565

SBAS411A – JUNE 2007 – REVISED NOVEMBER 2007

The DAC8565 has a 3-wire serial interface (SYNC,

The IOVDD pin powers the the digital input structures

SCLK, and DIN) compatible with SPI, QSPI, and

of the DAC8565. For single-supply operation, it can

Microwire interface standards, as well as most DSPs.

be tied to AVDD. For dual-supply operation, the IOVDD

See the Serial Write Operation timing diagram for an

pin provides interface flexibility with various CMOS

example of a typical write sequence.

logic families and should be connected to the logic

supply of the system. Analog circuits and internal

The write sequence begins by bringing the SYNC line

logic of the DAC8565 use AVDD as the supply

low. Data from the DIN line are clocked into the 24-bit

voltage. The external logic high inputs translate to

shift register on each falling edge of SCLK. The serial

AVDD by level shifters. These level shifters use the

clock frequency can be as high as 50MHz, making

IOVDD voltage as a reference to shift the incoming

the DAC8565 compatible with high-speed DSPs. On

logic HIGH levels to AVDD. IOVDD is ensured to

the 24th falling edge of the serial clock, the last data

operate from 2.7V to 5.5V regardless of the AVDD

bit is clocked into the shift register and the shift

voltage, assuring compatibility with various logic

families. Although specified down to 2.7V, IOVDD

shift register data. Once 24 bits are locked into the

operates at as low as 1.8V with degraded timing and

shift register, the eight MSBs are used as control bits

temperature

performance.

For

lowest

power

and the 16 LSBs are used as data. After receiving the

consumption, logic VIH levels should be as close as

24th falling clock edge, the DAC8565 decodes the

possible to IOVDD, and logic VIL levels should be as

eight control bits and 16 data bits to perform the

close as possible to GND voltages.

required function, without waiting for a SYNC rising

edge. A new write sequence starts at the next falling

edge of SYNC. A rising edge of SYNC before the

24-bit sequence is complete resets the SPI interface;

The DAC8565 output is asynchronously set to

no data transfer occurs. After the 24th falling edge of

zero-scale voltage or mid-scale voltage (depending

SCLK is received, the SYNC line may be kept LOW

on RSTSEL) immediately after the RST pin is brought

or brought HIGH. In either case, the minimum delay

low. The RST signal resets all internal registers, and

time from the 24th falling SCLK edge to the next

therefore, behaves like the Power-On Reset. The

falling SYNC edge must be met in order to properly

RST pin must be brought back to high before a write

begin the next cycle. To assure the lowest power

sequence starts. If the RSTSEL pin is high, the RST

consumption of the device, care should be taken that

signal going low resets all outputs to mid-scale. If the

the levels are as close to each rail as possible. (Refer

RSTSEL pin is low, the RST signal going low resets

to the Typical Characteristics section for Figure 36,

all outputs to zero-scale. RSTSEL should be set at

Figure 57, and Figure 79 (Supply Current vs Logic

power-up.

Input Voltage).

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