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INPUT SHIFT REGISTER

DAC8565

SBAS411A – JUNE 2007 – REVISED NOVEMBER 2007

DB21 = 0 and DB20 = 1: Single-channel update.

The

temporary

and

DAC

The input shift register (SR) of the DAC8565 is 24

corresponding to a DAC selected by DB18 and DB17

bits wide, as shown in Table 4. It consists of eight

are updated with the contents of SR data (or

control bits (DB23 to DB16) and 16 data bits (DB15

power-down).

to DB0). DB23 and DB22 should always be '0'. LD1

(DB21) and LD0 (DB20) control the updating of each

DB21 = 1 and DB20 = 0: Simultaneous update. A

analog output with the specified 16-bit data value or

channel selected by DB18 and DB17 updates with

power-down command. Bit DB19 must always be '0'.

the SR data; simultaneously, all the other channels

The DAC channel select bits (DB18, DB17) control

update with previously stored data (or power-down)

the destination of the data (or power-down command)

from temporary registers.

from DAC A to DAC D. The final control bit, PD0

DB21 = 1 and DB20 = 1: Broadcast update. If

(DB16),

selects

the

power-down

mode

the

DB18 = 0, then SR data are ignored and all channels

DAC8565 channels.

are

updated

with

previously

stored

data

(or

The DAC8565 also supports a number of different

power-down). If DB18 = 1, then SR data (or

load

commands.

The

load

commands

are

power-down) updates all channels. Refer to Table 5

summarized as follows:

for more information.

DB21 = 0 and DB20 = 0: Single-channel store. The

temporary register (data buffer) corresponding to a

DAC selected by DB18 and DB17 updates with the

contents of SR data (or power-down).

Table 4. DAC8565 Data Input Register Format

DB23

DB12

LD1

LD0

DAC Select 1

DAC Select 0

PD0

D15

D14

D13

D12

DB11

DB0

D11

D10

Table 5. Control Matrix for the DAC8565

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13-DB0

LD 1

LD 0

DAC Sel 1

DAC Sel 0

PD0

MSB

MSB-1

MSB-2...LSB

DESCRIPTION

Data

Write to buffer A with data

Data

Write to buffer B with data

Data

Write to buffer C with data

Data

Write to buffer D with data

Write to buffer (selected by DB17 and DB18) with

(00, 01, 10, or 11)

See Table 6

power-down command

Write to buffer with data and load DAC (selected by

(00, 01, 10, or 11)

Data

DB17 and DB18)

Write to buffer with power-down command and load

(00, 01, 10, or 11)

See Table 6

DAC (selected by DB17 and DB18)

Write to buffer with data (selected by DB17 and DB18)

(00, 01, 10, or 11)

Data

and then load all DACs simultaneously from their

corresponding buffers

Write to buffer with power-down command (selected by

(00, 01, 10, or 11)

See Table 6

DB17 and DB18) and then load all DACs

simultaneously from their corresponding buffers

Broadcast Modes

Simultaneously update all channels of DAC8555 with

data stored in each channels temporary register

Data

Write to all channels and load all DACs with SR data

Write to all channels and load all DACs with

See Table 6

power-down command in SR

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