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SM5956AF Datasheet(PDF) 1 Page - Nippon Precision Circuits Inc |
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SM5956AF Datasheet(HTML) 1 Page - Nippon Precision Circuits Inc |
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1 / 27 page ![]() SM5956A SEIKO NPC CORPORATION —1 6-channel Asynchronous Sample Rate Converter OVERVIEW The SM5956A is a digital audio signal, asynchronous sample rate converter LSI. It reads 6-channel 16/20/24- bit word length input data, and 16/20/24-bit word length output data. It also features a built-in digital deempha- sis filter, direct muting and digital audio interface output. FEATURES Functions I L/R 6-channel processing (2-channel stereo, 3-system processing) I Input sample rate range: 10kHz to 200kHz I Output sample rate range: 30kHz to 50kHz I Operating sample rate conversion ratio (fso/fsi)*1 • 0.45 to 4.41 (SCKSLN = L, 512fso operation) • 0.225 to 4.41 (SCKSLN = H, 768fso operation) *1: fsi = input sample rate fso = output sample rate I Asynchronous input timing and output timing clock inputs I System clock input • Input system clock: 1fsi (LRCI) • Output-system clock: 512fso/768fso (input on SCK) I Deemphasis filter function • IIR filter structure • 44.1kHz, 48kHz, 32kHz input sample rate fsi compatible I Direct mute function I Through mode • Input data passed directly to the outputs I Digital audio interface output • DIA input data undergoes sample rate conver- sion and is output biphase mark encoded I Output data clocks (LRCO, BCKO) • LRCO rate: 1fso • BCKO rate: 64fso (SCKSLN = L, 512fso operation) 48fso (SCKSLN = H, 768fso operation) • Slave mode: Data is output at a rate dictated by an externally input signal • Master mode: Sample rate is generated internally from the output-system clock, and supplied as an output I MCU interface • 3-wire serial interface I 5V tolerant inputs for direct connection to 5V devices I 3.3V single supply I Package: 48-pin QFP PINOUT (Top view) PACKAGE DIMENSIONS (Unit: mm) Note. Dimensions without tolerance are reference values. ORDERING INFORMATION Device Package SM5956AF 48-pin QFP 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 VDD DEEMN FS0 FS1 MCK MDT MLE DMUTEN THROUN SLAVEN OEDITON VSS VDD TEST0 TEST1 TEST2 TEST3 SCK VSS SCKSLN ERROR RSTN SELFN VSS 9 ± 0.4 7 ± 0.1 0.125 − 0.025 + 0.075 0.5 0 ~ 10 0.18 − 0.05 + 0.09 0.08 |
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