All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implemen-

tation.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

●

○

●

○

○

●

○

○

One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

SYMBOL

datai(7:0)

addr(1:0)

cs

rd

wr

datao(7:0)

out0

clk0

gate0

rst

out1

clk1

gate1

out2

clk2

gate2

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

rst

input Global reset

datai(7:0)

input Processor data bus (input)

addr(1:0)

input Processor address lines

cs

input Chip select

rd

input Processor read strobe

wr

input Processor write strobe

clk0

input Clock input for Counter 0

gate0

input Gate input for Counter 0

clk1

input Clock input for Counter 1

gate1

input Gate input for Counter 1

clk2

input Clock input for Counter 2

gate2

input Gate input for Counter 2

datao(7:0) output Processor data bus (output)

out0

output Output of Counter 0

out1

output Output of Counter 1

out2

output Output of Counter 2

BLOCK DIAGRAM

Counter 0

clk0

gate0

out0

Counter 1

Read/Write

Logict

Counter 2

rst

addr(1:0)

wr

rd

cs

Data Bus

Buffer

Control Word

Register

datai(7:0)

datao(7:0)

clk1

gate1

out1

clk1

gate1

out1

Read Write Logic

- The Read/Write Logic

accepts inputs from the system bus and gen-

erates control signals for the other functional

blocks of the D8254. ADDR(1:0) select one of

the three counters or the Control Word Regis-

ter to be read from/written into. A “low'' on the

RD input tells the D8254 that the CPU is

reading one of the counters. A “low'' on the

WR input tells the D8254 that the CPU is writ-

ing either a Control Word or an initial count.

Both RD and WR are qualified by CS; RD

and WR are ignored unless the 82C54 has