All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench

environment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single

FPGA

bitstream

and

ASIC

implementation.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time

restriction except One Year license where

time of use is limited to 12 months.

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Single Design license for

VHDL, Verilog source code called HDL

Source

Encrypted, or plain text EDIF called Netlist

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One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

CONFIGURATION

The following parameters of the D16550 core

can be easy adjusted to requirements of

dedicated

application

and

technology.

Configuration of the core can be prepared by

effortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- enable

- disable

- enable

- disable

- enable

- disable

- enable

- disable

- enable

- disable

- enable

- disable

APPLI C ATION

D16550

addr(2:0)

addr

latch

datai(7:0)

datao(7:0)

wr

rd

cs

intr

rxrdy

txrdy

out1

out2

EIA

Drivers

so

si

rts

dtr

dsr

dcd

cts

ri

baudclken

rclken

clk

rst

baudclk

rclk

CPU

addr

ale

datao(7:0)

datai(7:0)

we

rd

cs

int

Typical D16550 and processor connection is

shown in figure above.