All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench

environment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

●

Phone & email support

CONFIGURATION

The following parameters of the DRPIC166X

core can be easy adjusted to requirements of

dedicated

application

and

technology.

Configuration of the core can be prepared by

effortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

- 1-16

•

Number of hardware stack

levels

- default 8

- synchronous

- asynchronous

- used

- unused

- used / width

- unused

- used

- unused

- used

- unused

- used

- unused

- used

- unused

- used

- unused

SYMBOL

ramwe

ramoe

portao(7:0)

portbo(7:0)

portai(7:0)

portbi(7:0)

ramdatai(7:0)

t0cki

t1cki

clk

clkwdt

ramdatao(7:0)

rdaddr(8:0)

wraddr(8:0)

int

trisa(7:0)

trisb(7:0)

sleep

por

mclr

prgdata(13:0)

prgaddr(15:0)

portci(7:0)

portdi(7:0)

portco(7:0)

portdo(7:0)

trisc(7:0)

trisd(7:0)

docddatai

docddatao

docdclk

prgdatao(13:0)

prgwe

DoCD

ccp1i

ccp1o

rxdi

txcki

rxdo

txcko

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

clkwdt

input

Watchdog clock

por

input

Global reset Power On Reset

mclr

input

User reset

prgdata[13:0]

input

Data bus from program memory

ramdati[7:0]

input

Data bus from int. data memory

Int

input

External interrupt

t0cki

input

Timer 0 input

t1cki

input

Timer 1 input

ccp1i

input

Compare Capture channel input

rxdti

input

USART serial data input

txcki

input

USART serial clock input

portxi[7:0]

input

Port A, B, C, D input

docddatai

input

DoCD